Skip to main content
Scour
Browse
Getting Started
Login
Sign Up
You are offline. Trying to reconnect...
Close
Copied to clipboard
Close
Unable to share or copy to clipboard
Close
⚡ Cache Optimization
Data Locality, Cache-Friendly Code, Memory Hierarchy, Performance
Filter Results
Timeframe
Fresh
Past Hour
Today
This Week
This Month
Feeds to Scour
Subscribed
All
Scoured
184941
posts in
9.4
ms
A
Systematic
Evaluation of Novel and
Existing
Cache Side Channels
papers.cool
·
22h
💾
Cache Algorithms
Memory
Caching
:
RNNs
with Growing Memory
arxiv.org
·
22h
⚡
Cache-Aware Algorithms
Time is of the
essence
:
EBR
in High-Performance Databases
dev.to
·
21h
·
Discuss:
DEV
🧠
Memory Models
Optimizing
Recommendation Systems with
JDK
’s Vector API
netflixtechblog.com
·
1h
🔀
SIMD Programming
Optimal Heterogeneous Memory Configs for AI Tasks Under
Specified
Performance Metrics (Stanford,
UCSC
)
semiengineering.com
·
1d
🧠
Memory Hierarchy
Utility-Based Cache
Partitioning
: Making Shared
Caches
Smarter in Multi-Core Systems
dev.to
·
3d
·
Discuss:
DEV
🧠
Memory Hierarchy
The Hidden Optimization Behind Modern LLMs:
Grouped
Query
Attention Explained
pub.towardsai.net
·
10h
🔗
Memory Linearization
Show HN:
Benchmarking
the Keep memory system with
LoCoMo
keepnotes.ai
·
9h
·
Discuss:
Hacker News
🧠
Memory Models
High-Performance GPU Memory Transfer on AWS
Sagemaker
Hyperpod
research.perplexity.ai
·
5h
🌱
Green Threads
Quieno/izalloc
: Drop-in, dependency-free, minimal memory allocator in C that passes 42 Shool's norm.
github.com
·
1d
·
Discuss:
r/C_Programming
🧠
Memory Allocators
Data Driven Optimization of GPU efficiency for Distributed LLM
Adapter
Serving
arxiv.org
·
22h
⚡
Cache-Aware Algorithms
The ongoing quest for atomic
buffered
writes
lwn.net
·
4h
🔗
Memory Linearization
Right-sizes
LLM models to your system's RAM,
CPU
, and GPU
news.ycombinator.com
·
20h
·
Discuss:
Hacker News
🖥️
Minimal VMs
TurboSparse
Efficiency: Achieving 97% Parameter Sparsity in
Mixtral-47B
hackernoon.com
·
12m
🚀
Tokenizer Performance
Zero-Waste Agentic RAG: Designing
Caching
Architectures to
Minimize
Latency and LLM Costs at Scale
towardsdatascience.com
·
1d
📮
Message Queues
Efficient algorithms for mining top-k high
occupancy
itemsets
sciencedirect.com
·
23h
🌸
Bloom Indexing
Rare Huawei-ByteDance alliance unveils
RRAM
AI chip delivering 66x CPU speed at
ISSCC
2026
digitimes.com
·
10h
🔧
RISC-V
Ryzen 7
8745HS
(Zen 4
APU
, Phoenix): In-depth Performance Analysis
michaelstinkerings.org
·
8h
⚡
Performance
Beyond
Pandas
:
Architecting
High-Performance Python Pipelines
hackernoon.com
·
6h
📋
JSON Parsing
The volatile cache trap: Why turning off Windows buffer
flushing
will
silently
corrupt your SSD
howtogeek.com
·
8h
🧠
Memory Consistency
Loading...
Loading more...
Page 2 »
Keyboard Shortcuts
Navigation
Next / previous item
j
/
k
Open post
o
or
Enter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
g
h
Interests
g
i
Feeds
g
f
Likes
g
l
History
g
y
Changelog
g
c
Settings
g
s
Browse
g
b
Search
/
Pagination
Next page
n
Previous page
p
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc
Press
?
anytime to show this help